This invention relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device and, in particular, to a capacitor structure of a dynamic random access memory (DRAM) and a method of forming the capacitor structure thereof.
"Semiconductor" devices are fabricated from various materials which either electrically conductive, electrically nonconductive or electrically semiconductive. Silicon (Si), the most commonly used semiconductor material can be made conductive by doping it (introducing an impurity into the silicon crystal structure) with either an element such as boron (B) which has one less valence electron than silicon, or with an element such as phosphorus (P) or arsenic (As) which have one more valence electron than silicon. In the case of boron doping, electron "holes" become the charge carriers and the doped silicon is referred to as positive or P-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carriers and the doped silicon is referred to as negative or N-type silicon. If a mixture of dopants having opposite conductivity type is used, counter doping will result, and the conductivity type of the most abundant impurity will prevail. Silicon is used either in single-crystal or polycrystalline form. Polycrystalline silicon is referred to hereinafter as "polysilicon".
Various semiconductor memory devices are already known.
U.S. Pat. No. 5,041,887 issued Aug. 20, 1991 to Kumagai et al, entitled "SEMICONDUCTOR MEMORY DEVICE" described, a semiconductor memory device including dynamic memory cells each being comprised of one transistor having source and drain regions and one cell capacitor. The cell capacitor with a reduced junction leakage current comprises a MOS capacitor which is provided between a semiconductor substrate and a charge storage electrode disposed at a side wall of a trench through a first insulating film, and a stacked capacitor which is provided between the charge storage electrode and a capacitor plate electrode formed on a second insulating film covering the entire surface of the charge storage electrode. The equivalent silicon dioxide thickness of the first insulating film is thicker than that of the second insulating film, and the storage capacitance of the cell capacitor is rendered by a sum of the capacitance of the MOS capacitor and the capacitance of the stacked capacitor because these capacitors are electrically connected in parallel with each other.
U.S. Pat. No. 5,047,817 issued Sep. 10, 1991 to Eimori et al, entitled "STACKED CAPACITOR FOR SEMICONDUCTOR MEMORY DEVICE" and division of this patent, U.S. Pat. No. 5,180,683 issued Jan. 19, 1993 to Eimori et al, entitled "METHOD OF MANUFACTURING STACKED CAPACITOR TYPE SEMICONDUCTOR MEMORY DEVICE; INCREASED STORAGE CAPACITY", describe a semiconductor memory device which comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface 0f a semiconductor substrate. The stacked capacitor has a structure extending on a gate electrode and a word line through an insulator layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
U.S. Pat. No. 5,114,873 issued May 19, 1992 to Kim et al, entitled "METHOD FOR MANUFACTURING A STACKED CAPACITOR DRAM CELL", describes a method of manufacturing a semiconductor device which has a plurality of memory cells, each of which consists of a transistor and a stack capacitor. The method comprises the steps of: forming the transistor of a substrate and then depositing an interlayer insulating layer, and forming a design pattern of a first conductive layer by vertically etching it using a mask, horizontally overetching the pattern by using the etching process used for forming the pattern; depositing a first insulating film and then depositing the second conductive layer to the thickness needed to protect the first insulating film and interlayer insulating layer by applying the mask used in vertically etching the first conductive layer; additionally depositing the second conductive layer; forming a design pattern of the second conductive layer by vertically etching it using a mask; horizontally overetching the pattern of the second conductive layer; depositing the second insulating film and then depositing a third conductive layer to have the thickness to protect the second insulating film; vertically etching the third conductive layer and second insulating film by applying the etching mask of the second conductive layer; and additionally depositing the third conductive layer. The method attains larger effective capacitance in which a plate electrode layer surrounds even the lower surface of the storage electrode layer of the stack capacitor without using an extra mask.
U.S. Pat. No. 5,140,389 issued Aug. 18, 1992 to Hashimoto et al, entitled "SEMICONDUCTOR MEMORY DEVICE HAVING STACKED CAPACITOR CELLS", describes a semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angle with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.
U.S. Pat. No. 5,175,121 issued Dec. 29, 1992 to Choi et al, entitled "METHOD FOR MANUFACTURING A STACKED CAPACITOR DRAM SEMICONDUCTOR DEVICE", describes a method for manufacturing a semiconductor device which includes selectively doping an impurity into the surface of a semiconductor substrate. An insulating layer is deposited and selectively etched to form a contact hole through which an area of the impurity-doped region is exposed. An epitaxial layer is then grown using the exposed surface of the impurity doped region as a seed. Finally, a conductive layer is deposited upon the epitaxial layer.
U.S. Pat. No. 5,194,753 issued Mar. 16, 1993 to Kumagai et al, entitled "SEMICONDUCTOR MEMORY DEVICE", describes a semiconductor memory device including an array of dynamic memory cells. The cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately (1/2)n pitch where n represents a natural number greater than or equal to two.
With the large-scale integration in the DRAM, it is necessary to reduce the area of a memory cell in the DRAM. For that purpose, it has been attempted to enlarge the ratio of storage capacitance of the memory cell to the area of the memory cell. In this event, miniaturization has been facilitated in a contact hole. In particular, in the DRAM having a stacked capacitor (STC) structure, a C.O.B (Capacitor Over Bitline) cell structure has been adopted in a 16 Mbit DRAM. The C.O.B cell structure is a structure where a storage capacitor is formed upon a bit line in order to ensure the storage capacitance of the memory cell and to deal with noise between lines. In addition, with the miniaturization of the contact hole, a contact hole with a space on a side wall thereof has been designed.
In general, a semiconductor memory device such as the DRAM of stacked type comprises a plurality of memory cells each of which includes a switching transistor and a storage capacitor. The switching transistor has a gate electrode and a pair of source/drain regions. The gate electrode selectively coats or covers the surface of a semiconductor substrate such as a P-type Si substrate through a gate insulating layer. The pair of source/drain regions is formed on the surface portion on the semiconductor substrate with a channel region under the gate electrode inserted between the source/drain regions. The storage capacitor selectively coats or covers the surface of at least one interlayer insulating layer which coats or covers the switching transistor. The storage capacitor has a storage electrode, which consists, for example, of a polysilicon layer, for connecting with one of the source/drain regions through a contact hole.
In a conventional semiconductor memory device, the contact hole for electrically connecting the storage electrode with the above-mentioned one of the source/drain regions is formed on the above-mentioned one of the source/drain regions by an anisotropic dry etching process and an insulating spacer is formed on the inner side wall of the contact hole by another anisotropic dry etching process after a coating film with good step coverage is grown on the whole surface of the substrate.
In the manner which will later become clear as the description proceeds in conjunction with FIGS. 1A to 1C, a conventional method of forming the contact hole for electrically connecting the storage electrode with the above-mentioned one of the source/drain regions results in increasing of a junction leakage current in the contact portion between the switching transistor and the storage capacitor. This is because there is an insufficient diffusion of impurities to the P-type Si substrate in the vicinity of the above-mentioned one of the source/drain regions by diffusing phosphorus (P) in the polysilicon layer of the storage electrode due to a high aspect ratio. As a result, it is necessary to form an impurity diffusion layer using ion implantation after making the contact hole. However, it is difficult to perform sufficient ion implantation if the contact hole is made with the contact hole ranged to the gate electrode. This is because the ion implantation for decreasing the junction leakage current results in changing of a characteristic of the switching transistor. In addition, in the conventional method of forming the contact hole, crystal defects occurs in the above-mentioned one of the source/drain regions due to both the anisotropic dry etching process for forming the contact hole and the anisotropic dry etching process for forming the insulating spacer on the inner side wall of the contact hole. Accordingly, it is difficult to sufficiently decrease the junction leakage current, resulting in deterioration in a hold characteristic of the storage capacitor.